Program timing circuitry for central data processor of digital communications system

ABSTRACT

Circuitry is disclosed for monitoring the execution of programs in a central processor of a digital communications system. For recovery programs under the normal mode the program must &#39;&#39;&#39;&#39;punch in&#39;&#39;&#39;&#39; with a recovery program timer at designated intervals, or the circuitry generates a system error level signal. In a special mode, punch in may occur at any time prior to a designated time. Further, for programs other than recovery programs, an error bistable circuit monitors the output of a real time timer which is incremented every basic order time (i.e., machine cycle time) and which will cause the system to enter a recovery phase if it overflows prior to its being reset.

United States Patent 1191 Chang et a1.

1 1 PROGRAM TIMING CIRCUITRY FOR CENTRAL DATA PROCESSOR OF DIGITAL COMMUNICATIONS SYSTEM [75] Inventors: Gregory I. Chang, Oak Park; Rolfe E. Buhrke, La Grange Park; Donald L. Schulte, Oak Park; John A. Wilher, Elk Grove Village. all of I11.

[73] Assignee: GTE Automatic Electric Laboratories Incorporated, Northlake, I117 [22] Filed: Aug. 31, 1973 [21] App]. No.: 393,542

[52] U5. Cl. 340/172.5; 340/146.1 D [51] Int. Cl. t. G06F 1/04 [58] Field of Search 340/1725, 146.1; 444/1 [56] References Cited UNITED STATES PATENTS 3,623,011 11/1971 Baynard,1r. ct a1. 340 1715 3,623,017 11/1971 Lowell et a1. 340/1725 3.623.019 11/1971 Groth 340/1725 PERIPHERAL coumoutn I! TRIX EGISTER INSTRUCTION STORE 1 DATA CIRGJI'T TO OTHEH U 11's CENT 4L PROBE SSOR ACCESS cmcmr NPUT- OUTPUT CIRCUIT 1 Sept. 30, 1975 Primary Examiner-Gareth D. Shaw Assistant Eraminer-John P. Vandenburg Attorney, Agent, or Firm.lohn T. Winburn l 57] ABSTRACT Circuitry is disclosed for monitoring the execution of programs in a central processor of a digital communications system. For recovery programs under the nor mal mode the program must punch in" with a recovery program timer at designated intervals, or the circuitry generates a system error level signal. In a special mode, punch in may occur at any time prior to a designated time. Further, for programs other than recovery programs, an error bistable circuit monitors the output of a real time timer which is incremented every basic order time (1.0., machine cycle time) and which will cause the system to enter a recovery phase if it overflows prior to its being reset.

11 Claims, 39 Drawing Figures ACCESS TMKS PROCESSOR CONTROL CI RCUI? TO OTHEH PS UN! TS Sept. 30,1975

She

et 4 of 22 TIM/N6 GENERATOR CIRCUIT cp 50J CPI I rsc 1 LEVEL L ,52 MM ammnron MAC a cm. swlrcmrva "swrrcmm; CPAS 60c MC ssaw. CONTROL CONTROL SSBYL i 1 u MMC MCC emrcnms SWITCHING MCC pm 1 NETWORK NETWORK I p c L5! 51' I ncc rmms mum ace 1'! ME LEVELS LEVELS r! ME TO cPa r0 CP FIG 4 he MODE,D0,AND

READ/WRITE 3g usnonv AND c ISR PERIPHERAL MAC msmucnou um;

1%2w% 55 DPC CMPALCMU AND 0pc ozcooms gg MC CIRCUITS MMC 10c A REGISTER 53 AND CIRCUIT PLACE PLACE A6CEPT AND LEVELS ACCEPT fi-DPC I CONTROL cmcwrs gas RANSFER BUS .LEVELS TRANSFER CONTROL *0 PC CIRCUITS PROCESSOR CONTfiOL CIRCUIT (FCC) CONTROL CIRCUIT TLGC MMC ICC RC6 AND MAC (UP STATUS CIRCUIT IGONFIGURA TION Sheet 8 0f 22 Ila CPAL (BUS CONFIGURA TION) I l 100 (BUS I CONFIGURATION) 'rwc Mm: 100 Rcc AND me I (0P srArus) CONFIGURATION CONTROL Sept. 30,1975

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CONTROL CIRCUIT l CPAL \CPAL COM-'16 URATIOIV U.S. Patent MAC MICC I C M m mcww 0 PTC I'I'l-lll l'll'll l-Il lll l lll l 6C 0 IWW rec PM ccc roc RCO I00 I ma MMC mmrzlvmvcz ACCESS cmcu/r T66 P60 C06 I06 R60 ICC TMC "MC US. Patent Sept. 30,1975 Sheet 11 0f 22 3,909,795

NAND 88 as g;

GATE' "AND 870 t 850 GATE NA 0 HAND 86c GAT E GATE 86a qfl T5AL s B' e 85 mm) AND ATE "IGATE AND H NAND GATE GATE GATE 88 85 b 86 b MND ATE " AND NAND ATE GATE HAND GATE

FIG.|8

WAVEFOHRMS FAlLURE m 0 STATE min 4.0,. TBAL 5 I 4.! 5 T 5" GAUuSPF'OR BOTH FAILURES US. Patent Sept. 30,1975 Sheet 13 of 22 3,909,795

FIG 2O TLCC COUNTER CIRCUITS :"PLACE" EVEN COUNTER l 'PEAL PEG PEACH!) 93 FROM INPUT STAGE PEBCFH) F H T0 IMRB. 95d B I5 PESTLH) RESET To our ur n H POACHI) STAGE PLACE ODD C OUNTER POBCFU) I\POC TL L 3 POBCF I O IMRB. B I6 mom 'NPUT -"A ccEP EVEN COUNTER AEACF STAGE EBL AEBCF 25 L EBCF T0 IIMRB AOACF ACCEPT on c UNTER 0 AOBCF M AOBC I TO IMRB. Bl8

-C PACL FROM ITCCL T7PL momccg- RCFL =CPACL ITCCL T0 RESET COUNTERS, RCFL=OJ US. Patent Sept. 30,1975 Sheet 14 of 22 3,909,795

W FIG.2|

IPEAcP HAL FROM TLCC 1T0 TLEIF POSTL AESTL FROM ccc (DCPAL Fl G. 22

TIMING LEVEL ERROR INDICATING FLIP-FLOPITLEIF] FROM TLEL 7 Q 1- 82 TLEIF To TLCC (Egg- 1BRB.B27 OUTPUT I 1 STAGE 1 [REIFL E I I I Fl G. 23

TIMING DIAGRAM or TI.cc COUNTERS TIMING INTERVAL f I213 [HHS T7 KPEAL WITH 1 FL INPUT PESF=0 PEBL wITII I I I I PEACF 0R AE CF MAC SENSING POAL WITH I L I I POSF= o POBL WITH I If I PETF=0 INPUT FPoAcF 0R AOACF P086, 0R \ADBCF SAMPLED FOR TLEL OUTPUT MAC SENSING AT THE END OF TTPL on TTAL. THE OUTPUTS or ALL GGGNTER FLIP-FLOPS SHOULD BE "o' U.S. Patent Sept. 30,1975 Sheet 18 of 22 3,909,795

RECOVERY PFiQjRAM COUNTER REGISTER FLIP-FLOP (RPCR) 2 8: NAND NAND RPCRBINII FIG.27

GATE

T TO RPAOC NAND AND RPCR-BIMHI [RPCRAL 1 ATE GATE MULTIPLED TO 6 OTHER FLIP-FLOPS OF RPCR M=O THRU s FIG.28 RPCR ACCEPT LEvEL IRPCRAL) FROM TGc -W NANO RPCRAL 1 RPCR FROM RPTAP [RPTAF GATE GATE RPR ACCEPT LEvEL (RPR FROM TGc W NAND RPRAL [RPTAF GATE GATE 1 FIG.3O

RPR REsET LEV EL(RPRRL) SP NAND R NO RPRRLl'!) TORPR FROM DPC[SPR.B| DATE GATE ATE J ICCSL FROM Icc[ FIG.3|

MAC CONTROL FOR DISABLING RPT RAFL T0 RESET )RPTAFasPME SMGBL (D) AND NANO WL 1 TO ERROR FROM GATE GATE J MAC mOaBsO LEvEL CKT.

U.S. Patent Sept. 30,1975 Sheet 19 of 22 3,909,795

FIG. 32

HH OVERY PROGRAM COUNTER ADD-ONE C|RCU|T(RPAOC) RPAOCB (D6 RPJTE? amiss WW m4 -RPAOC. B054 Wm M3 FRQM RPCR RPAOCBGB To RPR W- 8 J C RPAOCBdJI RPCR B 'RPCRB RPRRL OVFL 

1. A recovery program timer system for a data processing system having a central data processor including processing circuits and maintenance circuits, an interrupt control circuit for generating an interrupt control circuit sequence level signal to start an interrupt cycle, and a recovery control circuit for generating an enable recovery program timing level signal when a recovery program is called, said timer responsive to said enable recovery program timing level signal to initiate a recovery program cycle, said timer comprising: recovery program register means for accumulating and storing signals representative of a count of machine cycles of said central processor; incrementing circuit means for incrementing the stored count signals in said recovery program register means each cycle time of said sentral processor, including overflow signal producing means, said interrupt control circuit sequence level signal initializing the incrementing circuit means to zero count; recovery program timer bistable circuit means responsive to said enable recovery program timing level signal for actuating said recovery program register means; and logic circuit means responsive to a recovery program punch-in signal and said overflow signal from said incrementing circuitry for generating a recovery program timing error level signal only if said punch-in signal and said overflow signal do not occur at the same time when said recovery program timer is operating in a normal mode.
 2. The system of claim 1 further comprising: real time timer means for accumulating and storing signals representative of the lapse of real time during the execution of non-recovery program in said central processor.
 3. The system of claim 1 wherein said recovery program timer further comprises special mode bistable circuit means responsive to a programmed signal for enabling said punch-in bit to occur at any time prior to a predetermined number of machine cycle times, thereby to reset said recovery program timer without generating said recovery program timer error level signal.
 4. The system of claim 1 wherein said central processor further comprises real time timer circuit means for accumulating signals representative of a real-time count of machine cycle times during the execution of non-recovery programs in said processor and for generating a real time timer error level signal when a predetermined number of machine cycles have occurred without program resetting; and real time error bistable means responsive to said real time timer error level signal for generating an output error signal representative thereof.
 5. The system of claim 4 wherein said incrementing circuit means overflow signal producing means is responsive to the output of said register means and generates an overflow signal when a predetermined count is exceeded and wherein said logic circuit means comprises exclusive or logic circuit means responsive to said punch-in signal and said overflow signal of said incrementing circuit means.
 6. The system of claim 1 wherein said incrementing circuit means comprises a recovery program counter register receiving the output of said recovery program register circuit means; and recovery program add one circuit means receiving the contents of said recovery program counter register for adding an increment of one thereto and for feeding the input of said recovery program register circuit means.
 7. The system of claim 6 further comprising bistable circuit means for disabling said recovery program timer circuit means in response to a program instruction, said bistable cIrcuit means being capable of disabling said recovery program timer circuit means in the normal mode only after a punch-in signal has occurred simultaneously with said overflow signal of said incrementing circuit means.
 8. The system of claim 1 further comprising circuit means for generating a recovery program timer error level signal when said punch-in signal occurs in any machine cycle other than said overflow signal.
 9. The system of claim 8 further comprising circuit means for generating said recovery program timer error level signal when said recovery program timer circuit means is reset prior to the end of a full recovery program cycle.
 10. The system of claim 9 further comprising special mode circuit means responsive to a special mode signal under program control, for permitting said punch-in signal to occur prior to said overflow signal of said incrementing circuit means without generating said recovery program timer error level signal.
 11. The system of claim 10 further comprising circuit means for generating said recovery program timer error level signal if said special mode circuit means is actuated at any time other than the end of a normal recovery program cycle. 